[석/박사 경력 인정] 삼성전자 DS부문 R&D분야 외국인 경력사원 채용

Job Positions and Qualifications

Common Eligibility Criteria

• Foreign nationals with no disqualifications for obtaining a visa or working in Korea
• Holders of TOPIK (Test of Proficiency in Korean) Level 3 or above
  ※ Scores obtained between September 3, 2022, and September 3, 2024, are accepted. Those without a language score can submit their results by January 2025.

Common Preferred Qualifications

• At least two years of relevant work experience after obtaining a bachelor’s degree
  ※ The duration of study will be recognized as work experience for those who have obtained or are expected to obtain a master’s or doctoral degree.

[Memory Division] Storage Architecture

Key Responsibilities

• Design of Computer Architecture and Storage System Architecture
• Performance Modeling, Simulation, and Analysis
• Design and development of Memory (DRAM/NAND) Controllers
• Design and development of Hardware/Software for Embedded Systems
• SOC front-end/back-end development
  • AMBA-based SOC design
  • Core Cluster (ARM, RISC-V) research/development

Eligibility Criteria

• Degree in Electrical Engineering, Semiconductor Engineering, or related fields

[Memory Division] Host System S/W

Key Responsibilities

• Research and development of Storage systems, Distributed Systems, Networks, Cloud, Servers
• Research and development of Storage Protocol Specs such as PCIe, NVMe
• Research and development of Data Center standard Specs
• Research and development of SSD performance analysis (host-to-device)
• Research and development of Data-Intensive technologies

Eligibility Criteria

• Degree in Electrical Engineering, Semiconductor Engineering, or related fields

[Memory Division] Firmware Development

Key Responsibilities

• Research and development of Storage Firmware
• Research and development of NVMe Host Interface
• Research and development of Embedded System Firmware
• Development of verification Firmware (HAL code development and guidance, optimization of FW performance using Emulator)

Eligibility Criteria

• Degree in Electrical Engineering, Semiconductor Engineering, or related fields

[Memory Division] S/W Architecture

Key Responsibilities

• Design and development of Embedded SW Architecture
• Research on performance analysis/modeling/simulation and optimization of Embedded SW
• Analysis and documentation of SRS (Software Requirement Specification)

Eligibility Criteria

• Degree in Electrical Engineering, Semiconductor Engineering, or related fields

[System LSI Division] Circuit Design

Key Responsibilities

• xPU HW Design
  • Design of MAC engine for NPU (NN operation optimization engine design)
  • Implementation of GPU core RTL
  • Implementation of CPU block (integration of clock & power management, bus components, debug subsystems, etc.)

Eligibility Criteria

• Degree in Electrical Engineering, Semiconductor Engineering, or related fields

[System LSI Division] Signal and System Design

Key Responsibilities

• Multimedia IP development
  • Development of Camera RTA (Real-time Algorithm) solutions
  • Development of Camera DDK
  • Development of Camera System SW
  • Development of Camera Solutions
  • Development of Camera Tuning Tools

Eligibility Criteria

• Degree in Electrical Engineering, Semiconductor Engineering, or related fields

[Foundry Division] Semiconductor Process Design

Key Responsibilities

• DFM and Yield Analysis
  • Optimization of Mask Tape Out and development of DFM solutions
  • Analysis of the correlation between process issues and yield and process improvement
• Device/SRAM Development
  • Development and analysis of devices/SRAM
  • Development and characterization of RF devices
• Advanced FEOL/BEOL Process Development
  • Understanding of advanced process technology and analysis of module-specific process issues
  • BEOL integration, Passive Device, Process Assumption/DR development and initial mass production support
  • Collaboration with module and unit processes to secure characteristics and yield of new products
• Next-Generation Process and eMRAM/eFlash/DDIC Process Development
  • Development of next-generation processes and HPC specialty (Si photonics) process development
  • Development and mass production of processes for eMRAM, eFlash, eRRAM, DDI, OLED products

Eligibility Criteria

• Degree in Electrical Engineering, Semiconductor Engineering, or related fields

[Foundry Division] Circuit Design

Key Responsibilities

• Design Technology
  • Development of advanced Digital design methodologies for leading-edge processes
  • Development of Chip design methodologies for Foundry
  • Development of Foundry EDA ECO and SW/ML
• Design Enablement
  • Design of DTCO & Standard cell libraries, building of ECO Libraries, and support for Foundry customers
  • Provision of SRAM and NVM Foundation IP
  • Development and customer support of SPICE models for all process devices
  • Development of PDK and ESD solutions
• Foundry Design Service
  • SoC Integration & Architecture
  • Physical Implementation/Integration/Design/Verification
  • Design Implementation/Verification and Design Service
  • Power/Signal Integrity and SW solutions
• IP Development
  • Development and verification of Security/Analog/Digital IP
  • Design of Serdes Architecture and Interface IP development
  • Ensuring IP quality and operating the ECO system

Eligibility Criteria

• Degree in Electrical Engineering, Semiconductor Engineering, or related fields

[Foundry Division] Evaluation and Analysis

Key Responsibilities

• Development of next-generation Test technology
  • Yield analysis, failure analysis, and development/evaluation of new processes
• Development and evaluation of Test programs
  • Development and evaluation of Test programs for Overseas Foundry products, SOC and ASIC products, LSI products
• Quality management and reliability evaluation
  • Management of process quality for mass-produced products
  • Customer Quality & Reliability
  • Reliability evaluation of Foundry-developed processes

Eligibility Criteria

• Degree in Electrical Engineering, Semiconductor Engineering, or related fields

[Semiconductor Research Center] Semiconductor Process Technology

Key Responsibilities

• Process Integration
  • Development of memory products (DRAM, Flash, New Memory, etc.) and system semiconductors (Logic, CIS, etc.)
  • Research on the architecture, structure, and integration of next-generation Memory/Logic/CIS, etc.
  • Yield prediction and improvement based on line data for each product
• Device Analysis
  • Development of next-generation semiconductor devices such as Transistors, Cell Design, etc.
  • Improvement of device characteristics through prediction, measurement, and data analysis of semiconductor device characteristics
  • Performance and yield improvement through device operation modeling and failure analysis

Eligibility Criteria

• Degree in Electrical Engineering, Semiconductor Engineering, or related fields

[Semiconductor Research Center] Semiconductor Process Design

Key Responsibilities

• Process Development
  • Securing and advancing the eight leading process technologies for semiconductor product development
  • Development of new process technologies for implementing new materials and next-generation semiconductor devices
  • Process management through monitoring of measurement data by module
  • Development of element technologies for improving development methodologies and processes
  • Development of materials for new precursors and next-generation semiconductors
• Analysis Technology
  • Development of defect inspection technology using Optic & E-beam, etc.
  • Analysis of defect environmental impact and physical property analysis of Memory and Logic products
  • Optimization of semiconductor manufacturing processes, equipment, and environment using Big Data-based production information

Eligibility Criteria

• Degree in Electrical Engineering, Semiconductor Engineering, or related fields

[Global Manufacturing & Infrastructure Group] Mechanical Development

Key Responsibilities

• Development of mechanical systems for robot control design to automate hazardous tasks
  • Development of robot system integration/control/recognition technology for automation of hazardous tasks
  • Development of mobile manipulator control and motion planning, multi-sensor fusion-based algorithms
  • Establishment of hardware systems required for automation in chemical analysis laboratories of supply facilities
  • Development of hardware systems for high-altitude work platforms as part of scaffolding replacement solutions

Eligibility Criteria

• Degree in Mechanical Engineering, Semiconductor Engineering, or related fields

[Global Manufacturing & Infrastructure Group] Infrastructure Quality Assurance

Key Responsibilities

• Conducting audits to establish/maintain QMS for construction projects
  • Monitoring the Quality Management System of contractors during Quality System Audits
  • Analysis of internal and external specifications and review of improvement plans
  • Reviewing the application of the Quality Management System by contractors/designers/supervisors
  • Technical and quality review of design, construction, specifications, new technologies, and cost items, and confirmation of suitability

Eligibility Criteria

• Degree in Mechanical Engineering, Semiconductor Engineering, or related fields

[Global Manufacturing & Infrastructure Group] EHS/Infrastructure Technology (Water Treatment)

Key Responsibilities

• Water treatment expert for water reuse and resource recovery in water systems
  • Development of water reuse technology by removing pollutants and micropollutants from wastewater
  • Development of technology for concentrating/crystallizing ionic pollutants
  • Development of processes for recycling and resource recovery/circulation of pollutants in wastewater
  • Development of technology for adsorption/decomposition/filtration of micropollutants and zero-discharge/no-emission technology

Eligibility Criteria

• Degree in Mechanical Engineering, Environmental Engineering, Semiconductor Engineering, or related fields

[Global Manufacturing & Infrastructure Group] EHS/Infrastructure Technology (Exhaust Treatment)

Key Responsibilities

• Development and analysis of new exhaust treatment technologies and identification of mechanisms
  • Development of greenhouse gas/air pollutant reduction technologies (catalysis, adsorption, membrane separation, plasma, photonic/electric treatment technologies)
  • Analysis of trends in new exhaust treatment technology development and development of new concept treatment technologies and advanced treatment technologies
  • Analysis of specific substances in exhaust systems and identification of treatment mechanisms (discovery of exhaust gas analysis tools)
  • Development of small scrubber materials and systems, performance evaluation, and localization of catalysts/adsorption materials

Eligibility Criteria

• Degree in Mechanical Engineering, Environmental Engineering, Semiconductor Engineering, or related fields

[Global Manufacturing & Infrastructure Group] EHS/Infrastructure Technology (Energy)

Key Responsibilities

• Development of energy-saving technologies for semiconductor infrastructure machinery/equipment/systems
  • Design of next-generation infrastructure/plant energy-saving systems and development of high-efficiency equipment
  • Development of problem-solving technologies related to Bulk Gas/HVAC
  • Basic design, FEED design, and design of rotating/machinery equipment for infrastructure/plants (clean rooms, related equipment, etc.)
  • Development of energy-saving roadmaps for HVAC based on knowledge of thermodynamics/heat transfer/fluid mechanics

Eligibility Criteria

• Degree in Mechanical Engineering, Environmental Engineering, Energy Engineering, Chemical Engineering, or related fields

[Manufacturing & Technology Division] Data Engineering

Key Responsibilities

• Data Engineering & Service
  • Implementation of measurement generation algorithms using physical sensors on equipment
  • Building a Big Data-based measurement analysis solution
  • Development of optimal process-measurement-yield impact prediction solutions using ML/DL/Foundation Models
  • Analysis and integration of yield analysis processes based on business process analysis methodologies
  • Implementation of integrated analysis system architecture
• Data Intelligence
  • Analysis of causes and control of yield anomalies caused by equipment and components
  • Establishment and systematization of yield analysis/improvement methodologies
  • Development and implementation of integrated yield prediction factor analysis systems
  • Development and implementation of central control systems for equipment
  • Development of process recipe-related analysis methods through Fault Detection Classification (FDC)

Eligibility Criteria

• Degree in Electrical Engineering, Industrial Engineering, Semiconductor Engineering, or related fields

[Manufacturing & Technology Division] Mechanical Development

Key Responsibilities

• Development of automation-related technologies for semiconductor manufacturing (Cobot/Robot, AGV & AMR, Digital Twin)
  • Specification and deployment of Cobot/Robot for FABs in clean rooms, securing of leading-edge technologies
  • Analysis of semiconductor equipment/process operation methods using Digital Twin technology and development of optimal solutions
  • Planning and operation of component logistics based on equipment PM schedules
  • Establishment and execution of integrated logistics plans for FAB/Factory, securing of leading-edge technologies
• Development of software for production equipment/systems for the construction/operation of automation systems
  • Development of a real-time data-based equipment automation platform
  • Development of AI-based optimal process condition exploration technology and equipment/process anomaly analysis technology
  • Collection/processing/storage and processing/analysis of large-scale data for mass production equipment/processes
• Development of customized sensors and applications for semiconductor process equipment
  • Development of sensor solutions/applications customized for on-site needs (mobile or installed)
  • Development of equipment/module diagnostic technology through sensor customization
  • Development of advanced equipment monitoring systems (e.g., AI-based real-time judgment technology)
• Development of automated Predictive Maintenance (PdM) for semiconductor equipment
  • Development of diagnostic technology and systems (e.g., measurement/diagnostic technology for part performance deterioration)
  • Development of equipment control technology (e.g., Fume monitoring and control systems, P/C control)
  • Judgment of equipment maintenance timing through physical model simulation and data-based analysis

Eligibility Criteria

• Degree in Electrical Engineering, Mechanical Engineering, Semiconductor Engineering, or related fields

[Manufacturing & Technology Division] R&D Technical Support

Key Responsibilities

• Fab Modeling for Digital Twin construction in semiconductor production sites
  • Analysis of production-related data such as Capacity, Output, Input, WIP, TAT, etc.
  • Fab Modeling based on wafer, equipment, infra, and process conditions
  • Planning process modeling for Fab operations, production changes, and decision-making
• Support for decision-making through simulation based on Fab Modeling
  • Management of baseline information (TAT, Capacity, etc.) required for simulation
  • Planning and development of simulation models that closely resemble actual semiconductor fabs
  • Construction of manufacturing optimization solutions that assist decision-making, such as productivity improvement, TAT reduction, etc.
• Expansion of coverage through the construction of Manufacturing Process-Based Systems
  • Analysis of production/planning processes and identification of problems
  • System integration for optimization of operations through simulation, logic changes, etc.

Eligibility Criteria

• Degree in Electrical Engineering, Semiconductor Engineering, or related fields

[Manufacturing & Technology Division] Foundry Equipment Development

Key Responsibilities

• Construction of Platform-based Autonomous Manufacturing environments
  • Establishment of a Process-Based System framework (PBS):Automation of all stages of major engineering activities, including PM/backup, interlock analysis/judgment/action, and process evaluation, definition and improvement of business processes, and design of systems/platforms
  • Identification and automation of on-site inefficiencies that require manual intervention
  • Definition and improvement of system inefficiencies based on Foundry business characteristics
  • Automation of qualitative engineer judgments based on AI/Machine Learning algorithms (interlock actions, anomaly maps, engineer alerts, etc.)
• Operation of Factory Simulation for Capa/Production Volume/Equipment Efficiency
  • Development of short-term simulations using What-if Simulation techniques
  • Development of mid/long-term simulations through the construction of FAB modeling
  • Implementation of Virtual FAB using simulator tools

Eligibility Criteria

• Degree in Electrical Engineering, Mechanical Engineering, Semiconductor Engineering, or related fields

[Manufacturing & Technology Division] Data Analysis

Key Responsibilities

• Setup of BF/DF/Macro inspection recipes and analysis of raw data for advanced nodes
• Physical property analysis using XPS, Raman, OCD, Ellipsometry
• e-Beam inspection, CD-SEM measurement setup, and data analysis

Eligibility Criteria

• Degree in Electrical Engineering, Semiconductor Engineering, or related fields

[Manufacturing & Technology Division] Solution Development

Key Responsibilities

• Development of Image Quality Enhancement Technologies
  • Development and application of Image resolution enhancement technologies
  • Development and application of noise reduction technologies
• Development of Key ROI Automatic Measurement Algorithms
  • Development and application of Image pre-processing and measurement technologies
  • Algorithm optimization
• Development of Image Classification and Detection Technologies
  • Review and application of AI-based image classification and detection technologies

Eligibility Criteria

• Degree in Electrical Engineering, Computer Engineering, Semiconductor Engineering, or related fields

[Manufacturing & Technology Division] Material Development

Key Responsibilities

• Development and quality improvement of semiconductor materials
  • Development/quality of Photo Resist materials, Hardmask materials
  • Development of Chemical, CMP materials (slurry for film polishing speed and selectivity control)
  • Development of Si Wafer, CVD/ALD/PVD Precursor, Metal materials
  • Development of high-purity GAS materials and refining technologies
• Research on greenhouse gas reduction materials and recycling technologies contributing to ESG management

Eligibility Criteria

• Degree in Electrical Engineering, Materials Engineering, Semiconductor Engineering, or related fields

[Manufacturing & Technology Division] Semiconductor Process Technology

Key Responsibilities

[CMP]

• CMP & Grinding Infra, Equipment, Materials Design, Management & Services
• Analysis of wafer/slurry behavior during CMP & Grinding processes and Data analysis
• Advanced Technology Sensing & Process Design
  • Development of process conditions for new equipment, new processes, and new materials
  • Development of materials (slurry, PAD), components (disk, grind wheel) technologies

[PHOTO]

• Development and management of Bonding Overlay process technology
  • Development of simulation for optimizing Align/Overlay Keys through measurement sampling algorithms
  • Development of automatic correction algorithms and judgment algorithms
  • Defect resolution and standardization of process conditions through yield/quality improvement
• Analysis of Bonding process issues and implementation of automation systems
  • Establishment and optimization of process automation systems through Big Data analysis
• Optimization of Wafer Photo operation to address BV NAND Warpage (Align/Leveling/CD variation)
• Optimization of Photo Edge Engineering in high-step environments

[CLEAN]

• Optimization of Wet/Dry Cleaning technology and processes related to Bonding
• Improvement and maintenance of production equipment hardware performance
  • Defect resolution, evaluation of optimal conditions, equipment diagnostics, and alignment (modifications, improvements)
  • Maintenance of Bonding PRE CLN new equipment

[CVD]

• Optimization of new Bonding technology
  • Optimization of process conditions considering quality, productivity, and cost for each Bonding Process (SAP: Plasma Treatment / Rinse / ABM: Bonding)
  • Acquisition of technical assets in areas outside the core technology of CVD within the Bonding Process Module→ Integration of proprietary technologies for Rinse (clean), ABM (Photo alignment management)

[Flash YE]

• Improvement of process conditions, characteristics, and yield for mass production and large-scale production of BVNAND

Eligibility Criteria

• Degree in Electrical Engineering, Semiconductor Engineering, or related fields

[Manufacturing & Technology Division] Device Development

Key Responsibilities

• DRAM Device Development
  • Research on improving and enhancing the characteristics of Cells and Capacitors
  • Research on optimizing and improving Transistor operation performance
  • Verification of characteristics risks for mass-produced products and proposal of optimal schemes considering quality and manufacturability

Eligibility Criteria

• Degree in Electrical Engineering, Semiconductor Engineering, or related fields

[Manufacturing & Technology Division] Evaluation and Analysis

Key Responsibilities

• Improvement and management of yield for leading-edge mass-produced products
  • Management of process and yield for products of Foundry customers, technical customer support
  • Development of semiconductor device module processes to secure stable and competitive mass production baseline processes
  • FAB data analysis and issue improvement through statistical and Big Data analysis and Smart factory analysis
• Device/SRAM
  • Securing product windows by improving performance, manufacturability, and variation during the development life-cycle
  • Implementation and optimization of appropriate device characteristics based on understanding of processes, design, and product characteristics to maximize product competitiveness and yield

Eligibility Criteria

• Degree in Electrical Engineering, Semiconductor Engineering, or related fields

[Manufacturing & Technology Division] Manufacturing Software

Key Responsibilities

• Development of automation solutions for equipment PM tasks
  • Control of robots for automatic replacement of large/heavy parts
  • Control of automated equipment for fastening/adjustment of parts
  • Control of automated systems for transporting parts/tools
  • Control of automated equipment setup systems
• Development of Fab operation automation system software
  • Control of autonomous transport robot systems within Fab
  • Development of control and operation software for automated equipment
  • Development of monitoring software integrated with upper-level systems
  • Development of GUI and communication software
• Development of Autonomous Robot Software
  • Development of autonomous driving software
  • Development of manipulation technology based on learning
  • Development of vision-based image processing algorithms
  • Development of recognition/perception technologies
  • Development of Imitative Learning
• Development of Fab Equipment Platform Software
  • Development of Auto Teaching, Auto Leveling software
  • Development of airflow control and robot control software

Eligibility Criteria

• Degree in Electrical Engineering, Computer Engineering, Semiconductor Engineering, or related fields

[Manufacturing & Technology Division] Platform Development

Key Responsibilities

• Development of equipment platforms and design verification solutions
  • Development of test equipment operation software and improvement of Image Processing performance
  • Development of automated software for verification of design/circuit data

Eligibility Criteria

• Degree in Electrical Engineering, Computer Engineering, Semiconductor Engineering, or related fields

[TSP Group] Solution Development

Key Responsibilities

• Development of Package Thermal Solutions
  • Simulation and Measurement of thermal resistance (Package Level)
  • Temperature prediction in customer environments (SiP Level)
  • Thermal characteristic analysis for each CoW, D2W Platform
  • Simulation and Measurement of thermal performance for Mobile AP
  • Thermal characteristic analysis for each FOWLP, 3D IC Platform
  • Thermal design and verification of Thermal Test Vehicles
• Development of High-Performance Computing Package Thermal Solutions for Servers
• Development of Thermal Solutions for Server Package Products
  • Development of Liquid Cooling technology
  • Development of Package Embedded Vapor Chamber technology

Eligibility Criteria

• Degree in Electrical Engineering, Mechanical Engineering, Semiconductor Engineering, or related fields

[TSP Group] CAE Simulation

Key Responsibilities

• Package Mechanical Simulation
  • Calculation of Package structural dynamics and fluid dynamics
• Process Modeling and Simulation
  • Process Modeling Tests and Simulations involving complex multi-physics
  • Nonlinear, viscous, phase change, or composite material Modeling and Mechanical Metrology
• Structural and Process Optimization
  • Automation and optimization of Numerical Simulation procedures
  • Statistical Modeling and optimization based on Machine Learning and Deep Learning

Eligibility Criteria

• Degree in Electrical Engineering, Semiconductor Engineering, or related fields

[TSP Group] Package Development

Key Responsibilities

• Optimization of SI and PI characteristics for composite Memory+Logic products
  • GDDR, EDP, Mobile AP, HPC ASIC
• Technical support for SI/PI to global customers (Apple, Google, Intel, etc.)
• Acquisition of SI/PI Solutions and DM development
  • Development of PI Solutions for High-Power products
  • Development of new Design Methodologies for SI, PI
• Schematic Design, Module Design (SiP, Chiplet)
• CPI (Chip Package Interconnection)
• Package Design tasks
  • Establishment of competitive specs considering customer environments
  • Discovery of solutions to enhance product competitiveness
  • Package Layout considering Design Rules
  • Determination of Package Architecture and specifications
  • Electrical, Mechanical, Thermal characteristic Sign-off
  • Substrate, MK, POD drawings
  • DVR stage Process operation
  • Package Test and Failure Analysis

Eligibility Criteria

• Degree in Electrical Engineering, Mechanical Engineering, Semiconductor Engineering, or related fields

[TSP Group] Evaluation and Analysis

Key Responsibilities

• Analysis of defective samples from Electrical Tests and identification of defect causes
• Analysis Techniques
  • eFA (Electrical Failure Analysis): Analysis technique to predict the location and mode of defects using design information of Chip and Test result data from defective samples
  • pFA (Physical Failure Analysis): Structural analysis technique using specialized analysis equipment such as SEM, TEM, FIB to verify the defect mode by analyzing the physical structure of defective samples
• Development of semiconductor failure analysis technologies
  • Development of FI/Non-destructive/analysis technologies and investment in equipment
  • Discovery and investment in structural/chemical/characteristics analysis technologies
• Evaluation/Analysis of PKG products and material properties
  • Analysis of behavior (thermal, physical/chemical) according to the structure/material properties of packaging products
  • Identification of the correlation between product behavior and defects (e.g., Short occurrence due to Warpage changes caused by CTE differences)

Eligibility Criteria

• Degree in Electrical Engineering, Mechanical Engineering, Semiconductor Engineering, or related fields

[Innovation Center] Platform Development

Key Responsibilities

• Development, deployment, and operation of AI/Data/DevOps/Services
  • Development of LLM (Large Language Model) training, Prompt Engineering, CoT (Chain-of-Thought), etc.
  • Development of AI application technologies to solve challenges in design, development, manufacturing, and quality domains
  • Data analysis and feature engineering, development of data preprocessing and data pipelines for training
  • Development of AI algorithms utilizing images, videos, and text
  • Development of systems using AI/ML/DL models
  • Deployment and operation of DevOps tools, build/CI/CD infrastructure
  • Deployment and operation of internal knowledge service infrastructure and collaboration tools, such as search, chatbot, Q&A
  • Development and operation of Data platform services for development/manufacturing/management, Data Lake/DW construction
  • Design of conceptual/logical data modeling, data flow, and large-scale data processing systems
  • Improvement of data quality/data pipeline optimization
  • Design, construction, and operation of self-analytics tools, data parallel and distributed processing tools
  • Construction/design of data governance implementation system
• Development, deployment, and operation of AI/Data/DevOps/Services
  • Metadata management, establishment of data integration/loading/distribution policies, and management processes
  • Construction/development/operation of data governance implementation system architecture
  • Development and operation of lineage/metadata/quality management functions
  • Deployment and operation of DevOps tools, development/operation of build/CI/CD infrastructure
  • Development/operation of collaboration tools
  • Development/operation of internal knowledge service infrastructure, such as search, chatbot, Q&A
  • Development/operation of data platform services for development/manufacturing/management, Data Lake/DW
  • Development of conceptual/logical data modeling, data flow, and large-scale data processing systems
  • Improvement of data quality/data pipeline optimization

Eligibility Criteria

• Degree in Electrical Engineering, Computer/SW Engineering, Semiconductor Engineering, or related fields

[Innovation Center] R&D Technical Support

Key Responsibilities

• IT Architecture strategy and operations based on EA (Enterprise Architecture)
  • Planning and execution of Architecture management systems for Application/Technical/Data Architect areas from the perspective of Enterprise Architecture
  • Establishment/operation of IT strategy roadmap to achieve business goals
  • Planning and implementation of Architecture strategy and framework
  • Analysis and optimization of Architecture, Gap analysis
  • Establishment of Architecture principles and governance criteria, and review of IT projects based on them
  • Providing advice on IT technology trends and cases
  • Standardization and assetization of department Architecture information
  • Collaboration to understand and improve the IT Architecture status of overseas subsidiaries
  • Proposal and review of IT projects for overseas subsidiaries based on the department's IT strategy
• DX change management and Gen. AI policy establishment/technology evaluation
  • Planning, operation, diagnosis, and monitoring of DX change management programs
  • Establishment of Gen.AI policies and sensing of Gen.AI technology
  • Establishment and operation of LLM evaluation systems
  • Consulting/field innovation project support and operation for Gen.AI and Digital Tools
  • Planning and promotion of Digital Re-Skilling/Up-Skilling programs
  • Planning and promotion of DX Communication for executives and employees (company-wide) and business divisions

Eligibility Criteria

• Degree in Electrical Engineering, Computer/SW Engineering, Semiconductor Engineering, or related fields

[Innovation Center] Manufacturing Software

Key Responsibilities

• Development of TCAD simulation for semiconductor manufacturing
  • Optimization of electrical characteristics of various semiconductor products (memory/logic/analog/etc.)
  • Reliability simulation of devices (HCI, Off-state, TDDB, BTI, Isolation BV) and DFT/MD simulation for extracting characteristics of amorphous semiconductor materials
  • Topography simulation (Etch/PVD/CVD/ALD/CMP) and mechanical stress analysis under conditions of friction, cracks, delamination, and scale-bridging modeling
  • Surface reaction simulation using traditional methods (ab-initio, md w/ reactive force fields, mlip, tbmd, kmc)
• Development of AI solutions for semiconductor manufacturing
  • Data analysis based on explainable AI architecture
  • Development of Generative AI algorithms to improve simulation usability
  • Development of vision and interatomic potential algorithms for analyzing and optimizing semiconductor manufacturing processes
  • Development of image-based 3D structure measurement and visualization techniques
• Process automation and optimization based on data and algorithms
  • Design of logins, metrics, and models to enhance system productivity
  • Implementation of analysis methods, algorithms, and operation of software systems for library utilization
  • Construction of process phenomenon analysis systems, analysis of engineer requirements, and system enhancement through effectiveness verification

Eligibility Criteria

• Degree in Electrical Engineering, Computer/SW Engineering, Semiconductor Engineering, or related fields

[Innovation Center] Platform Architecture

Key Responsibilities

• Development of a Micro-Service Architecture Platform for large-scale Manufacturing Data processing
  • Development of a Micro-Service-based platform for large-scale Manufacturing Data processing
  • Integration of various open source (Kafka, Redis, Zookeeper, etc.) into the framework
  • Research on advanced technologies to improve the quality of the software platform
  • Software structure design/analysis/refactoring and performance/availability improvements

Eligibility Criteria

• Degree in Electrical Engineering, Computer/SW Engineering, Semiconductor Engineering, or related fields

[Innovation Center] System Development

Key Responsibilities

• Design, construction, and operation of Hyper-Scale CAE Simulation infrastructure services
  • Design/construction and operation of HPC Schedulers (LSF, UGE, PBS, etc.) for efficient resource management
  • Application parallelization/optimization, scheduling optimization
• Building a DB for computing resource utilization analysis and designing AI/ML-based analysis and prediction models
  • Cost efficiency through resource optimization using data analysis techniques and the development of demand forecasting models
  • Analysis, planning, and efficiency of computing resource demand, planning and operation of billing systems
• Governing the use of Public Cloud for HPC within the DS division
  • Design, construction, and operation of On-Prem./Public Cloud infrastructure for HPC, strategy formulation, establishment/optimization of operational SOPs, scaling response, performance evaluation and optimization, cross-deployment of new technologies (IaC-based automation, optimization of On-Prem./Public integration, cost optimization, expansion of instances/regions)
  • Strategic cooperation and communication with major cloud providers (CSP: AWS, Azure, SDS)
• Design/construction/operation of Cloud IT Infra
  • Design of Cloud (Private/Public/Hybrid) Enterprise Architecture
  • Design/construction/operation of Server, Storage, and Network Infra based on virtualization
  • Development of automated software for Hyper-Scale Cloud Infra operations (Infrastructure as Code)
  • Development of software for operating Cloud Native services based on Kubernetes
• Research on optimizing network structure for global cloud-based networks and on-premise backbone networks
  • Research and strategy formulation for applying SD-WAN technology
  • Research on MPLS-based optical core virtualization and BGP-based on-premise backbone network technology
  • Analysis of global and local network traffic based on Layer 3
  • Research on Policy Based Routing and QoS technologies for global cloud network services

Eligibility Criteria

• Degree in Electrical Engineering, Computer/SW Engineering, Semiconductor Engineering, or related fields

[SAIT] Semiconductor Process Technology

Key Responsibilities

• Development of new devices and thin films for next-generation Flash memory
  • Development of ALD thin films for Flash memory devices
    • Development of oxide and nitride thin films required for VNAND Flash structures
    • Selection of precursors for selective deposition of oxide and nitride thin films
    • Optimization through analysis of defects and traps in oxide and nitride thin films
  • Development of new schemes and implementation of characteristics for next-generation Flash memory devices
    • Suggesting material development directions for optimizing memory operation
    • Development and implementation of memory device schemes through ion migration
    • Development of unit devices required for neuromorphic devices based on non-volatile memory

Eligibility Criteria

• Degree in Electrical Engineering, Materials Engineering, Semiconductor Engineering, or related fields

[SAIT] Circuit Design

Key Responsibilities

• Development of Analog/Digital computational acceleration systems
  • Development of computational circuit/architecture structures and performance analysis
    • Design of efficient analog/digital computational acceleration circuits and architectures
    • Development of analog/digital computational acceleration systems and test chips
    • Simulation and chip performance evaluation

Eligibility Criteria

• Degree in Electrical Engineering, Computer Engineering, Semiconductor Engineering, or related fields

[SAIT] Signal and System Design

Key Responsibilities

• Photonic Computing Architecture/Algorithm
  • AI network design for photonic computing
  • Research and development of high-performance computing architecture

Eligibility Criteria

• Degree in Electrical Engineering, Computer Engineering, Semiconductor Engineering, or related fields

[SAIT] CAE Simulation

Key Responsibilities

• Design and development of 2D material layered structure circuits and architecture / Semiconductor device TCAD and process simulation
  • Design of 2D material logic gate circuits and development of 3D layered structure architecture
    • Construction of circuit design and architecture design environments
    • Development and improvement of design methodologies
    • Development of circuit layouts considering Lab/Fab process compatibility
    • Optimization and analysis of PPA (Power, Performance, Area)
  • TCAD simulation and compact model development for 2D material-based devices
    • Construction of 2D device simulation environments
    • Consideration of physical parameters at the atomic level
    • Modeling of I-V and C-V responses and implementation of compact models
    • Close collaboration with the Integration team to ensure alignment with actual devices
  • Thermal-fluid analysis expert for optimizing CVD, ALD systems

Eligibility Criteria

• Degree in Electrical Engineering, Computer Engineering, Semiconductor Engineering, or related fields

[SAIT] Semiconductor Process Design

Key Responsibilities

• Research and development of Wafer-level Metamaterials and Metasurfaces
  • Design and development of Metamaterials and Metasurfaces
    • Design and development of optical metamaterial, metasurface devices
    • Design and development of acoustic metamaterial, metasurface devices
  • Setup and experimental analysis of wafer-level measurement systems
    • Optical: Measurement related to imaging, spectrography, interferometry
    • Ultrasonic: Imaging and analysis of ToF signals
  • Nano-fabrication: Fabrication of meta-structures based on dielectric and metal materials
    • Fabrication of metasurface and metamaterial structures
    • Integration of meta-structures with process technology and analysis of process characteristics

Eligibility Criteria

• Degree in Electrical Engineering, Computer Engineering, Semiconductor Engineering, or related fields

‍